During testing of a unit under test, real-time systems for rapid-prototyping communicate to the unit under test via input/output boards (I/O-boards) connected to an expansion bus of the real-time target hardware. If, for example, the target hardware is PC-compatible, the expansion bus may be a PCI (peripheral component interconnect) bus. PCI is available in various mechanical form factors: standard PCI, PMC, CompactPCI, and PC/104+. The slowest component of a real-time target application will almost always be the code that accesses I/O boards via the bus (PCI). Each single 32-bit read or 32-bit write access to an I/O board via a 32 bit/33 MHz PCI bus takes approximately 0.8 μs, which is a very long time compared to the instruction execution time on a 1 GHz CPU, a read or write time from/to the first or second level cache, or even RAM access time.
The design of a high-performance real-time system will therefore try to minimize the number of PCI bus accesses to an I/O board in order to reduce overall latency associated with accessing that I/O-board. The bus accesses are usually initiated by an I/O driver, which is the interface layer between the application layer (software) and the physical layer (the PCI bus and the I/O board, respectively). An optimized I/O driver will therefore have a minimal amount of software function calls leading to bus accesses. On the other hand, the number of necessary bus accesses is also dependent on the given hardware architecture of the I/O-board. This means that overall I/O latency is influenced by both hardware (the I/O-board) and software (the I/O-driver) and only an approach which takes both into account will eventually lead to a low-latency implementation.
An I/O connectivity found almost in any real-time application is the analog to digital converter (ADC). Analog to digital converters are circuits used to convert signals from the analog domain, where the signals are represented by continuous quantities, to the digital domain, where the signals are represented by discrete numbers. This I/O-type is necessary to access analog sensor signals, such as those output from pressure sensors. From a latency perspective, analog to digital converter technology is an expensive I/O-operation, because the conversion process of the ADC has first to be initiated by the I/O driver. Then, the I/O driver waits on the conversion of an analog signal to digital form to complete. After completion of the conversion, the I/O driver reads the converted value from the ADC on the I/O-board. For each step, at least one PCI bus access is necessary, which significantly increases the time required to access information from the I/O board.
Most real-time applications require more than one analog input channel to be available. For example, most commercially available analog-to-digital I/O-boards are multi-channel boards, which sixteen channels being typical. However, most of these I/O-boards include one single analog-to-digital converter onboard for all of the channels. During conversion, the numerous analog input channels must be electronically multiplexed before leading to the ADC. The conversion of multiple analog input channels is thus a sequential process, rather than a parallel process, which leads to very high overall latency.
Two analog-to-digital conversion methods are currently commercially available in ADC I/O-boards. The first method, which is generally preferred for sample-based controls applications, is a software-initiated conversion method. FIG. 1 is a flowchart illustrating the steps involved in performing a software-initiated conversion method in the prior art. In the software-initiated conversion method, the real-time algorithm of the real-time target hardware is time-triggered by a timer source independent of the ADC I/O-board (asynchronous). When the algorithm requires a digital representation of an analog signal in an analog channel of the I/O board, the associated I/O driver initiates the conversion of the signal in step 12 and then waits for the ADC to finish the conversion in step 14. After conversion is complete, the driver reads the converted value directly from the ADC I/O-board in step 16. In step 18, the driver reads the digital signal into the real-time algorithm. Steps 12-18 are repeated whenever the real-time algorithm needs the digital representation of the analog signal. For multi-channel boards with a single ADC, this process may be required to be repeated for each channel (sequential conversion). Some board designs try to minimize the associated latency with the help of channel queue and conversion FIFO buffers. For multi-channel boards with one ADC per channel, this process can be done in parallel. Nevertheless, the software-initiated conversion method leads to a high latency implementation, because the I/O driver has to wait on the conversion to finish before reading the value from the ADC.
The second type of conversion method, which is generally preferred for frame-based DSP and/or Data Acquisition applications, is a hardware-initiated conversion method. FIG. 2 is a flowchart illustrating the steps involved in performing a hardware-initiated conversion method in the prior art. In the hardware-initiated conversion method, a clock source on the ADC I/O-board is programmed to output a conversion signal with a certain period in step 22. The conversion signal periodically initiates the analog to digital conversions of signals in the I/O board in step 24. The converted signals are then passed to the I/O driver in step 26, which feeds the digital values to the real-time algorithm in step 28. The hardware-initiated conversion has the advantage that the I/O driver does not have to initiate the conversion and therefore does not have to wait on the conversion to be completed. However, with the hardware-initiated conversion, the real-time algorithm no longer controls the time of a conversion, and initiating a conversion at any given time is no longer possible. As a consequence, it is usually the completion of the conversion of all channels which will then eventually trigger the execution of a cycle of the real-time application that uses the converted signals. This leads to a synchronous execution scheme, which can be less than ideal for certain applications, such as controls applications. In addition, the commercially available ADC I/O-board of this type are optimized for acquiring (converting) multiple sets of the chosen channels at a given rate and returning the converted values as so-called frames. For sample-based applications, with a frame size of one, these boards introduce either high latency or long group delay because of interrupt latency time or DMA (direct memory access) setup time, i.e., the time a DMA controller and destination needs to setup a DMA transfer.